Sequential Logic Design
========================
In contrast to combinational logic design, sequential logic design does not only depend on current inputs
but but also on prior inputs. The information stored within a circuit are often called state variables.
In this section, we will consider some simple circuits like latches and flip-flops that allow to store state variables
and are the building blocks for more complex synchrounous sequential logic circuits.
SR-Latch
-----------------------------
In the first experiment, we will consider one of the most basic sequential circuits called SR-latch, which is depicted in :numref:`fig:SRLatch`.
.. figure:: /Sequential_Logic_Design/pics/SRLatch.svg
:name: fig:SRLatch
:align: center
Sequential SR-Latch circuit
It consists of two cross coupled NOR gates and allows to store and control one bit of information as a state variable.
as indicated by the truth values in :numref:`tab:SRLatch`.
.. _tab:SRLatch:
.. table:: Truth-table for the SR-Latch circuit depicted in :numref:`fig:SRLatch`.
:align: center
+---------------------+-----------------------------+---+---+---+
| :math:`S` | 0 | 0 | 1 | 1 |
+---------------------+-----------------------------+---+---+---+
| :math:`R` | 0 | 1 | 0 | 1 |
+---------------------+-----------------------------+---+---+---+
| :math:`Q` | :math:`Q_{prev}` | 0 | 1 | 0 |
+---------------------+-----------------------------+---+---+---+
| :math:`\bar{Q}` | :math:`\overline{Q_{prev}}` | 1 | 0 | 0 |
+---------------------+-----------------------------+---+---+---+
In this experiment, we will use the `Digital <https://github.com/hneemann/Digital>`_ tool to investigate its behavior by examining its wavefront.
.. admonition:: Tasks
#. Use the `Digital <https://github.com/hneemann/Digital>`_ tool to draw the SR-Latch Circuit shown in :numref:`fig:SRLatch`
#. Add appropriate labels to the inputs and outputs of the circuit.
#. Add a wavefront (Bauteile/IO/Messwertegraph) to the drawing.
.. figure:: /Sequential_Logic_Design/pics/Digital-Wavefront.png
:name: fig:Digital-Wavefront
:align: center
SR-Latch circuit with wavefront.
#. Run your circuit and examine the wavefront for various combinations of inputs.
.. figure:: /Sequential_Logic_Design/pics/Digital-Wavefront-SR_latch.png
:name: fig:Digital-Wavefront_SR_latch
:align: center
Wavefront for a running SR-Latch circuit.
#. Validated that it produces the correct output as stated in :numref:`tab:SRLatch`.
#. In the menu (Bearbeiten/Verhalten fixierenden Testfall erstellen), you will also find the option to specify certain test cases.
#. Use this option to fix various different inputs to test the behaviour of the circuit.
.. figure:: /Sequential_Logic_Design/pics/Digital-Wavefront-SR_latch_fixing.png
:name: fig:Digital-Wavefront_SR_latch_fixing
:align: center
Creating test cases by fixing a combination of different inputs.
#. Once you are done with fixing suitable inputs, you can run the test case and examine the resulting truth table and wavefront.
.. hint::
Press the play button with the green check symbol.
.. figure:: /Sequential_Logic_Design/pics/Digital-Wavefront-SR_latch_result.png
:name: fig:Digital-Wavefront_SR_latch_result
:align: center
Resulting wavefront and truth table for a test case with different fixed inputs.
#. Save and submit all important information, namely, the circuit (as ``SR-latch.dig``), the truth table (as ``SR-latch.csv``), and
the wave front (as ``SR-latch.svg``).
D-Latch
------------------
Note that the inputs :math:`S` and :math:`R`
of the SR-Latch are used to reset (if :math:`R=1`), to set (if :math:`S=1`) or to output (if :math:`S=R=0`) the previous value of the state variable at :math:`Q`.
In this experiment, we will examine an extension of the SR-Latch circuit called D-Latch.
Similar to the SR-Latch, the D-Latch circuit has two inputs (:math:`D` and :math:`CLK`) and two outputs (:math:`Q` and :math:`\bar{Q}`) as depicted in :numref:`fig:DLatch`.
.. figure:: /Sequential_Logic_Design/pics/DLatch.svg
:name: fig:DLatch
:align: center
Sequential D-Latch circuit
In contrast to the SR-Latch, the input :math:`CLK` of the D-Latch now controls when the state should change and the input :math:`D` acts as a data input determining what the next state variable shall be - compare :numref:`tab:DLatch`.
.. _tab:DLatch:
.. table:: Truth-table for the D-Latch circuit depicted in :numref:`fig:DLatch`.
:align: center
+---------------------+-----------------------------+---+---+
| :math:`CLK` | 0 | 1 | 1 |
+---------------------+-----------------------------+---+---+
| :math:`D` | :math:`X` | 0 | 1 |
+---------------------+-----------------------------+---+---+
| :math:`Q` | :math:`Q_{prev}` | 0 | 1 |
+---------------------+-----------------------------+---+---+
| :math:`\bar{Q}` | :math:`\overline{Q_{prev}}` | 1 | 0 |
+---------------------+-----------------------------+---+---+
.. admonition:: Tasks
#. Use the `Digital <https://github.com/hneemann/Digital>`_ tool to draw the D-Latch Circuit using the SR-Latch from the previous experiment
as depicted in :numref:`fig:DLatch`.
#. Add appropriate labels to the inputs and outputs of the circuit besides a wavefront to the circuit.
#. In contrast to the previous experiment, we will now add an test environment (Bauteile/Sonstige/Testfall) to the circuit.
This allows to encode different input settings for evaluating the circuit and validating its correctness
(right click on the green ``Test`` item and press on ``Permanent Bearbeiten``).
.. figure:: /Sequential_Logic_Design/pics/Digital-Wavefront-D_latch_test.png
:name: fig:Digital-Wavefront_D_latch_test
:align: center
Creating a test environment for a circuit.
#. As shown in :numref:`fig:Digital-Wavefront_D_latch_encode`,
the different settings for each labeled item of the circuit are encoded (columnwise) in the text field.
Here, the first row is used to assign each column to a specific circuit item.
The following rows describe the different values to be tested for each item in a step, where
1/0 correspond to true/false and x represents an undefined value.
.. hint ::
Use undefined values X if you are not sure what an output will be.
.. figure:: /Sequential_Logic_Design/pics/Digital-Wavefront-D_latch_encoding.png
:name: fig:Digital-Wavefront_D_latch_encode
:align: center
Encoding a combination of different inputs in the test environment.
#. Once you are done with encoding the test environment, you can run the test case (Tests ausführen) and examine the resulting truth table and wavefront.
.. figure:: /Sequential_Logic_Design/pics/Digital-Wavefront-D_latch_result.png
:name: fig:Digital-Wavefront_D_latch_result
:align: center
Results of the test and corresponging waveform of the test environment.
#. Save and submit all important information, namely, the circuit (as ``D-latch.dig``), the test file with your encoding (as ``D-latch.txt``), the test result (as ``D-latch.csv``) and the wave front (as ``D-latch.svg``).
D-Flipflop
----------
As a last example, we will examine D-Flipflop circuits as depicted in :numref:`fig:DFlipflop`.
They are almost identical to the D-Latches from the previous experiment but are edge-triggered.
Namely, the D-Latch is transparent when the control bit is set, i.e., :math:`CLK=1`, whereas the D-Flipflop circuit
copies the value of the data input :math:`D` to the output :math:`Q` on the rising edge of :math:`CLK`.
To see this effect, we will compare the wavefront of the sequential D-Latch circuit and the D-Flipflop circuit to see this difference.
.. figure:: /Sequential_Logic_Design/pics/DFlipflop.svg
:name: fig:DFlipflop
:align: center
Sequential D-Flipflop circuit
.. admonition:: Tasks
#. Draw the D-Flipflop circuit using the D-Latch circuits from the previous experiment as shown in :numref:`fig:DFlipflop`.
#. Add a seperate D-Latch circuit to your drawing
and connect both circuits (D-Flipflop and D-Latch) to the same inputs (:math:`CLK` and :math:`D`).
#. Add appropriate labels to the seperate outputs of the two circuits, for example, :math:`Q_{Flipflop}` and :math:`Q_{Latch}`.
#. Use the test environment with the following inputs to show the difference between both circuits.
.. hint::
Assign undefined values to the outputs.
.. figure:: /Sequential_Logic_Design/pics/DLatchvsDFlipflop.svg
:name: fig:Digital-Wavefront_D_latch_vs_DFlipflop
:align: center
Wavefront for the inputs:math:`CLK` and :math:`D`.
#. Save and submit all important information, namely, the circuits (as ``D-Latch_vs_D-Flipflop.dig``),
the truth table (as ``D-Latch_vs_D-Flipflop.csv``), and the wave front (as ``D-Latch_vs_D-Flipflop.svg``).