Riptide is a finite-volume tsunami solver that runs as an interactive web application. Tsunami simulations typically run on compute clusters and require specialized software and careful setup. Riptide lowers this barrier: it runs directly in the browser, and a few clicks are enough to explore tsunami scenarios and build an intuition for how earthquakes can generate tsunamis.

Earthquakes can be placed along subduction zones on a 3D globe, and the resulting tsunami can be observed as it propagates within the selected region. Five presets based on historical earthquakes (Tōhoku 2011, Sumatra-Andaman 2004, Valdivia 1960, Maule 2010 and Alaska 1964) provide ready-made starting points, but users can also select their own region. For a closer analysis, they can place virtual tide gauges and follow the recorded water-level time series while the simulation runs.

Riptide’s simulation core is written in C++ and uses an f-wave solver for the shallow water equations. It is compiled to WebAssembly and runs in a background thread. The globe and the simulated waves are rendered with WebGL2, and the interface is built with React. The simulation runs on bathymetry from the GEBCO 2026 global grid, with fault geometry (depth, strike, dip) taken from the USGS Slab2 subduction model. From the chosen magnitude, the app estimates rupture dimensions using scaling laws and derives the average slip from the seismic moment. The Okada model then uses these parameters to compute the initial vertical displacement of the seafloor.

Riptide was developed as a student project by Mika Brückner, Yannik Köllmann and Jan Vogt as part of the Tsunami Lab in the summer term of 2026.

Earlier this year, we published Hello XDNA!, our guide to programming the neural processing units in AMD Ryzen AI chips. We have now updated its XDNA2 example so that key dimensions are supplied at runtime instead of fixed in the assembly code. The same assembly implementation can therefore handle a range of supported tensor shapes.

New step-by-step diagrams make the design easier to follow. They show how the kernel divides the calculation, shares its limited on-chip storage, and overlaps arithmetic with data movement. We also replaced the earlier fixed-size instruction schedule after discovering a subtle conflict at the accumulator write port that could silently discard a write.

Beyond the kernel example, the update expands and corrects our inferred instruction-set tables, fixes the BFP16 format description, improves the assembly listings, and addresses smaller errors and terminology issues throughout the site. Read the updated XDNA guide, check out the full changelog, or explore the sources and benchmarks.

AMD’s Ryzen AI chips contain XDNA neural processing units, unique spatial dataflow architectures with VLIW cores and dedicated matrix instructions. We are documenting these microarchitectures in detail: from XDNA1’s BF16 4×8×4 matrix operations at 256 FLOPs/cycle to XDNA2’s BFP16 8×8×8 operations at 1024 FLOPs/cycle. Our website covers the ISA, register files, operation latencies, and hand-optimized assembly kernels. The kernels achieve 398 BF16 GFLOPS (86% of peak) on an XDNA1 compute tile and 1760 BFP16 GFLOPS (95% of peak) on an XDNA2 tile. If you are interested in low-level NPU programming, check out the sources as well.