11. Control Unit

Section 10 covered almost the entire datapath of the single cycle core developed in this class. The unfinished core used in Section 10.2 is (with some limitations) able to execute the following instructions:

  • LDR (immediate)

  • STR (immediate)

  • ADD (immediate)

  • SUB (immediate)

  • AND (immediate)

  • ORR (immediate)

  • ADD (shifted register)

  • SUB (shifted register)

  • AND (shifted register)

  • ORR (shifted register)

However, we have seen that it is burdensome to use our core in this version: For every instruction we had to set the control signals RegSrc, RegW, ImmType, AluSrc, AluCtrl, MemW and Mem2Reg manually. This lab introduces a control unit which sets these flags for us based on the decoded instruction. Next, we introduce a set of new instructions which allow us to run code with PC-relative branching.

The lab is split into two parts. In Section 11.1, we’ll use a given decoder which derives the control signals and add it to our core. Next, Section 11.2 adds support for branching by introducing the instructions B.cond, ADDS, SUBS and ANDS to the datapath and control unit.

11.1. Decoder

We partially discussed the control decoder ctrl_inst_decode.dig in the lectures. In this part of the lab we’ll have another look at the decoder and integrate the decoder into our core’s design.

Tasks

  1. Briefly explain how the decoder derives the two control signals AluSrc and AluCtrl from the 32 instruction bits.

  2. Integrate the decoder into the unfinished core given by part_4_shifted_register.dig.

  3. Rerun the simple program in Listing 10.2.1 and provide respective SVG exports when the clock is low.

11.2. PC-relative Branching

Now, lets add another important piece to our core: Support for PC-relative branching. As already seen in Section 8 conditional code execution heavily utilizes jumps relative to the current value of the program counter.

Section 10.1 went one step further and we learned that bits 0-3 of B.cond are used to encode condition codes. The condition codes tell us which of the PSTATE register’s NZCV bits have to be set such that the program counter is modified by B.cond. If the condition is not satisfied, we simply execute the next instruction at address PC+4. Further, bits 5-23 hold the 19-bit immediate which encodes the PC-relative offset in the +/-1MB range.

Our targeted support for PC-relative branching requires us to utilize the NZCV flags which the ALU of our single cycle design returns. Until this point, they were simply hanging in the void and ignored by us. Following the Arm architecture, the condition flags are stored in the PSTATE register and only modified by flag-setting instructions. Support for B.cond and enabling our core for the flag-setting counterparts of the data processing instructions ADD, SUB and AND completes the PC-relative branching extension of our core:

../_images/bcond.svg

Fig. 11.2.1 Illustration of the intermediate single cycle core. The core supports B.cond in the datapath and has a control unit which sets RegSrc, RegW, ImmType, AluSrc, AluCtrl, MemW and Mem2Reg.

../_images/single_cycle_core.svg

Fig. 11.2.2 Illustration of this class’s final single cycle core covering the control unit and datapath.

Tasks

  1. Enable the datapath of Section 11.1’s enhanced single cycle core for B.cond. Follow Fig. 11.2.1 by adding the control signal PcOff to your design.

  2. Enhance the control decoder by providing the following outputs:

    • Cond: instruction bits which hold the condition codes.

    • FlagSet: high only if the input Inst is a flag-setting instruction, low otherwise.

    • Branch: high only if the input Inst is a B.cond instruction, low otherwise.

    Add a test case which thoroughly tests the new parts of your decoder.

  3. Add the PC Control logic which contains a 4-bit register holding the NZCV flags. PC Control should do the following:

    • Update the internal register’s NZCV bits on rising edges of the clock if input signal FlagSet is asserted. The register’s bits should be set to the data input NZCV.

    • Set the output signal PcOff to high if 1) the input signal Branch is asserted and 2) the internal register’s NZCV flags fulfill the condition encoded in the input bits Cond. In all other cases the output signal PcOff is low. It is sufficient to support the following variants of B.cond: b.eq, b.ne, b.lt, b.gt and b.al.

  4. Showcase your final design by running the example in Listing 10.1.3. Ignore the ret instruction.