11. Control Unit

Section 10 already covered part of the single-cycle core’s datapath being developed in this course. The complete datapath of the developed core is (with some limitations) able to execute the following instructions:

  • LDR (immediate)

  • STR (immediate)

  • ADD (immediate)

  • SUB (immediate)

  • AND (immediate)

  • ORR (immediate)

  • ADD (shifted register)

  • SUB (shifted register)

  • AND (shifted register)

  • ORR (shifted register)

We have seen that using our core in this version is cumbersome: For every instruction, we have to set the control signals RegSrc, RegW, ImmType, AluSrc, AluCtrl, MemW and Mem2Reg manually. This lab introduces a control unit that sets these signals for us based on the decoded instruction. Next, we will introduce a set of new instructions that allow us to run code with PC-relative branching.

The lab is split into two parts. In Section 11.1, we will use a provided decoder that derives the control signals and integrate it into our core. Next, Section 11.2 adds branching support by introducing the instructions B.cond, ADDS, SUBS, and ANDS to the datapath and control unit.

11.1. Decoder

We partially discussed the control decoder ctrl_inst_decode.dig in the lectures. In this part of the lab, we will have another look at the decoder and integrate it into our core’s design.

Listing 11.1.1 Simple program comprising five instructions.
 orr x0, xzr, #7
 and x1, x1, xzr
 add x2, x0, #3
 add x3, x1, #4
 sub x0, x2, x3

Tasks

  1. Briefly explain how the decoder derives the two control signals AluSrc and AluCtrl from the 32 instruction bits.

  2. Integrate the decoder into the unfinished core given by part_4_shifted_register.dig.

  3. Run the program in Listing 11.1.1 and provide respective SVG exports when the clock is low.

11.2. PC-relative Branching

Now, let us add another important piece to our core: support for PC-relative branching. As already seen in Section 8, conditional code execution heavily utilizes jumps relative to the current value of the program counter.

Section 10.1 went one step further, and we learned that bits 0–3 of B.cond are used to encode condition codes. The condition code field tells us which of the PSTATE register’s NZCV bits have to be set such that the program counter is modified by B.cond. If the condition is not satisfied, we simply execute the next instruction at address PC+4. Further, bits 5–23 hold the 19-bit immediate that encodes the PC-relative offset in the +/-1MB range.

Supporting PC-relative branching requires us to utilize the NZCV flags that the ALU of our single-cycle design returns. Until this point, they were simply unconnected and ignored. Following the Arm architecture, the condition flags are stored in the PSTATE register and only modified by flag-setting instructions. Support for B.cond and the flag-setting counterparts of the data processing instructions ADD, SUB, and AND completes the PC-relative branching extension of our core:

../_images/bcond.svg

Fig. 11.2.1 Illustration of the intermediate single-cycle core. The core supports B.cond in the datapath and has a control unit which sets RegSrc, RegW, ImmType, AluSrc, AluCtrl, MemW and Mem2Reg.

../_images/single_cycle_core.svg

Fig. 11.2.2 Illustration of this class’s final single-cycle core covering the control unit and datapath.

Tasks

  1. Enable the datapath of the enhanced single-cycle core from Section 11.1 for B.cond. Refer to Fig. 11.2.1 when adding the control signal PcOff to your design.

  2. Enhance the control decoder by providing the following outputs:

    • Cond: instruction bits which hold the condition codes.

    • FlagSet: high only if the input Inst is a flag-setting instruction, low otherwise.

    • Branch: high only if the input Inst is a B.cond instruction, low otherwise.

    Add a test case that thoroughly tests the new parts of your decoder.

  3. Add the PC Control logic that contains a 4-bit register holding the NZCV flags. PC Control should do the following:

    • Update the internal register’s NZCV bits on the rising edge of the clock if the input signal FlagSet is asserted. The register’s bits should be set to the data input NZCV.

    • Set the output signal PcOff to high if (1) the input signal Branch is asserted, and (2) the internal register’s NZCV flags satisfy the condition encoded in the input bits Cond. In all other cases, the output signal PcOff is low. It is sufficient to support the following variants of B.cond: B.EQ, B.NE, B.LT, B.GT, and B.AL.

  4. Showcase your final design by running the example in Listing 10.1.3. Ignore the RET instruction.