1. Combinational Logic Design

Boolean expressions can be represented in three different ways:

as a logical formula,

as a truth table, or

as a logical circuit build from the list of symbols given in Fig. 1.1.

Fig. 1.1 Logical gate symbols to draw combinational circuits

For example, the simple boolean expression with three variables

(1.1) $Y = \overline{B}*\overline{C}+A*\overline{B}$

is also represented by the logical circuit depicted in Fig. 1.2 and the truth values stated in Table 1.1.

Fig. 1.2 Circuit for the expression in Eq. (1.1) and the values stated in Table 1.1.

Table 1.1 Truth-table for the simple example given by Eq. (1.1) with minterms.
A	0	0	0	0	1	1	1	1
B	0	0	1	1	0	0	1	1
C	0	1	0	1	0	1	0	1
Y	1	0	0	0	1	1	0	0
minterms	$\bar{A}\bar{B}\bar{C}$	$\bar{A}\bar{B}C$	$\bar{A}B\bar{B}$	$\bar{A}BC$	$A\bar{B}\bar{C}$	$A\bar{B}C$	$AB\bar{C}$	$ABC$

Hint

Note that a logical formula is derived from the truth table by summing all minterms, i.e.,

(1.2) $Y = \overline{B}*\overline{C}+A*\overline{B}=\bar{A}\bar{B}\bar{C}+A\bar{B}\bar{C}+A\bar{B}C.$

1.1. Min-Term

In the first example, we will derive logical expressions that yields the same output for values given in a truth table.

Table 1.1.1 Truth-table for the unknown circuit.
A	0	0	1	1
B	1	0	X	X
C	X	X	0	1
Y1	1	0	1	0
Y2	0	0	1	1
Y3	0	0	0	1

Hint

X are Don’t cares, i.e. values that can be either true (1) or false (0).

Tasks

Derive an equivalent logical expressions for the outputs Y1,`Y2`, and Y3 from the truth table stated in Table 1.1.1.
Evaluate the three expressions for all possible inputs to derive a new truth table.
Use both truth tables to validate the correctness of your expressions.
Save your truth table (in csv-format as min_term.csv) and formula (as min_term.txt)

1.2. DIGITAL

In this experiment, we will draw and inspect our first combinational circuit using the Digital tool. The circuit represents the simple XOR expression of two inputs and one output given by

(1.2.1) $Y = A \bigoplus B.$

The truth values for this expression are stated in Table 1.2.1.

Table 1.2.1 Truth-table for the XOR expression stated in Eq. (1.2.1).
A	0	1	1
B	1	0	1
Y	1	1	0

Tasks

Open the Digital tool draw the circuit. Therefore, add one XOR gate, two inputs and one output to the workspace by choosing the correct items from the menu (Bauteile/Logisch and Bauteile/IO) - compare Fig. 1.2.1.

Fig. 1.2.1 Workspace to draw circuits and menu to add items.
Use the mouse (left-click) to connect the XOR gate with the inputs and output - compare Fig. 1.2.2.

Fig. 1.2.2 Drawing connections between the XOR gate and the in-/outputs.
Label the inputs and outputs (right-click on the item) and insert an appropriate name for the item - compare Fig. 1.2.3.

Fig. 1.2.3 Assigning labels to the in-/outputs.
Run your circuit (press play button) and test if it produces the correct results by activating different combinations of the inputs - compare Fig. 1.2.4.

Fig. 1.2.4 Running and testing the circuit.
The Digital tool also provides various options to analyse, synthesise,… a drawn circuit - compare Fig. 1.2.5.

Fig. 1.2.5 Menu to analyse, synthesis,… the circuit.
Use the analyse option to derive the truth table for your circuit - compare Fig. 1.2.6.

Fig. 1.2.6 Truth table of the circuit derived by the analyse option.
Save and submit the circuit besides the truth table (as csv-file) using the names XOR.dig and XOR.csv, respectively.

1.3. XOR

In this experiment, we will draw a reformulated combinational circuit using the Digital tool. The original circuit represents the simple XOR expression of two inputs and one output given by the XOR expression in (1.2.1) with the truth table stated in Table 1.2.1.

Tasks

Use the truth table to design a logical circuit that only consists of AND, OR, and NOT gates.
Draw your circuit in the Digital tool.
Use the analyse option to derive the truth table for your circuit.
Use the truth tables to validate that your circuit yields the correct results.
Save and submit the circuit using the name XOR_new.dig besides its formula (as XOR_new.txt).

1.4. XOR3

In this experiment, we will develop a combinational circuit for the XOR3 expression

(1.4.1) $Y = A \bigoplus B \bigoplus C$

with the following truth table:

Table 1.4.1 Truth-table for the XOR3 expression stated in Eq. (1.4.1).
A	0	0	0	1	1	1	1
B	0	1	1	0	0	1	1
C	1	0	1	0	1	0	1
Y	1	1	0	1	0	0	1

Tasks

Use the truth table to design a logical circuit that only consists of AND, OR, and NOT gates.
Use the analyse option (F9, Analyse/Analyse) from the Digital tool to derive the truth table for your circuit.
Use the truth tables to validate that your circuit yields the correct results, i.e., check that the original and new circuit produce the same outputs.
Save and submit the circuit using the name XOR3_new.dig besides its formula (as XOR3_new.txt).

1.5. Half Adder Circuit

In this experiment, we will derive a logical circuit for the half adder logic shown in Fig. 1.5.1. In contrast to the depicted circuit, the new circuit will only uses AND, OR, and NOT gates.

Fig. 1.5.1 Half Adder circuit using an XOR gate

Tasks

Draw the circuit depicted in Fig. 1.5.1 using the Digital tool.
Use the analyse option to derive the truth table for the circuit.
Based on this truth table, design a new equivalent circuit that only uses AND, OR, and NOT gates.
As before, use the truth tables to validate the equivalence of both circuits.
Save and submit both circuits (as half_adder_orig.dig and half_adder_new.dig) besides their truth tables (in csv-format as half_adder_orig.csv and half_adder_new.csv).

1.6. Full Adder Circuit

Similar to the half adder, we will derive a logical circuit for the full adder logic shown in Fig. 1.6.1 that only uses AND, OR, and NOT gates.

Fig. 1.6.1 Full Adder Circuit using XOR gates

Tasks

Draw the circuit depicted in Fig. 1.6.1 using the Digital tool.
Use the analyse option to derive the truth table for the circuit.
Based on this truth table, design a new circuit that only uses AND, OR, and NOT gates.
As before, use the truth tables to validate the equivalence of both circuits.
Save and submit both circuits (as full_adder_orig.dig and full_adder_new.dig) besides their truth tables (in csv-format as full_adder_orig.csv and full_adder_new.csv).

1.7. 2-Bit Adder

In this experiment, we will develop a combinational circuit for a 2-Bit adder that has four inputs (A1, A0, B1, B0) and three outputs (Y1, Y0, C) with the truth values stated in Table 1.7.1.

Table 1.7.1 Truth-table for the 2-bit adder circuit to be designed.
A1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1
A0	0	0	0	1	1	1	1	0	0	0	0	1	1	1	1
B1	0	1	1	0	0	1	1	0	0	1	1	0	0	1	1
B0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1
Y1	0	1	1	0	1	1	0	1	1	0	0	1	0	0	1
Y0	1	0	1	1	0	1	0	0	1	0	1	1	0	1	0
C	0	0	0	0	0	0	1	0	0	1	1	0	1	1	1

Tasks

Use several copies of the full adder circuit from the previous experiment to design the 2-bit adder circuit using the Digital tool as indicated in the schematic

Fig. 1.7.1 2-bit adder schematic using full adder circuits.

Hint: You can select (parts of) a circuit on the workspace (click the left mouse button, hold the mouse button, adapt selection square and then release the mouse button) and copy-paste items using the menu (Bearbeiten/Kopieren and Bearbeiten/Einfügen) or keyboard short-cuts (CTRL-C and CTRL-V).
Use the analyse option to derive the truth table for your designed circuit and validate its correcntess.
Save and submit the circuit (as 2bit_adder.dig) besides its truth table (in csv-format as 2bit_adder.csv).